Wideband 240-GHz Transmitter and Receiver in BiCMOS Technology With 25-Gbit/s Data Rate

Abstract

In this paper, a fully integrated wideband 240-GHz transceiver front-end, supporting BPSK modulation scheme, with on-chip antenna is demonstrated in SiGe:C BiCMOS technology with f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> = 300/500 GHz and local backside etching option. Within the transmitter, the upconversion is provided by fundamental mixing using a modified Gilbert cell mixer driven by a multiplier-by-eight local oscillator (LO) chain. The transmitter achieves a 3-dB RF bandwidth of 35 GHz with a saturated output power of -0.8 dBm. The down converter is equipped with a mixer first architecture. The mixer is designed utilizing a transimpedance amplifier as load for enhanced noise and bandwidth performance. For dc-coupled receiver, two dc offset cancellation loops are implemented within the receiver chain. It achieves a 3-dB RF bandwidth of 55 GHz, minimum single-sideband noise figure (SSB NF) of 13.4 dB, and a gain of 32 dB with 25-dB gain control. A wideband on-chip double-folded dipole antenna and an on-board optical lens are utilized to demonstrate a wireless link achieving 20- and 25-Gb/s data rates at bit error rates (BERs) of 6.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> and 2.2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> , respectively, across a distance of 15 cm. The transmitter and receiver consume 375 and 575 mW, respectively, which correspond to power efficiencies of 15 pJ/bit for the transmitter and 23 pJ/bit for the receiver. They occupy a silicon area of 4.3 and 4.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.