IEEE Transactions on Software Engineering · 2018 · 23 citations · 44 references
EngineeringComputer ArchitectureComputational ComplexityGpu ComputingArray ComputingHigh-performance ArchitectureComputer DesignArray SizesParallel ComputingCombinatorial OptimizationComputational GeometryConstruction TimesDesignComputer EngineeringComputer ScienceGpu ArchitectureHardware AccelerationArray ConstructorParallel Programming
We present a configurable, hybrid, and parallel covering array constructor, called CHiP. CHiP is parallel in that it utilizes vast amount of parallelism provided by graphics processing units (GPUs). CHiP is hybrid in that it bundles the bests of two construction approaches for computing covering arrays; a metaheuristic search-based approach for efficiently covering a large portion of the required combinations and a constraint satisfaction-based approach for effectively covering the remaining hard-to-cover-by-chance combinations. CHiP is configurable in that a trade-off between covering array sizes and construction times can be made. We have conducted a series of experiments, in which we compared the efficiency and effectiveness of CHiP to those of a number of existing constructors by using both full factorial designs and well-known benchmarks. In these experiments, we report new upper bounds on covering array sizes, demonstrating the effectiveness of CHiP, and the first results for a higher coverage strength, demonstrating the scalability of CHiP.
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Optimization by Simulated Annealing
Scott Kirkpatrick, C. D. Gelatt, M.P. Vecchi · Science · 1983 · 44K citations
Numerical Analysis, Large-scale Global Optimization, Computational Science +15
Cooling Schedules for Optimal Annealing
Bruce Hajek · Mathematics of Operations Research · 1988 · 1.2K citations