Low-Noise High-Linearity 56Gb/s PAM-4 Optical Receiver in 45nm SOI CMOS

Abstract

A 56Gb/s PAM-4 linear optical receiver with low noise and high linearity is presented. The fully integrated receiver comprises a transimpedance amplifier (TIA), a variable gain amplifier (VGA), an output buffer, auxiliary analog loops and on-chip bias circuitry. As will be shown, low noise and high linearity often contradict each other, thus both the TIA and VGA implement novel gain control techniques for linear operation while realizing low noise design, making them favorable for PAM-4 signal amplification. Designed and implemented in 45nm SOI CMOS technology, the receiver accomplishes state-of-the-art input-referred noise current of 1.8μArms, 74.4dB transimpedance gain and 23GHz bandwidth while consuming 37mW. The dynamic range achieved is 29dB, enabling large input overload of 0.8mA for PAM-4 compliant signaling.