A 0.009 mm² Wide-Tuning Range Automatically Placed-and-Routed ADPLL in 14-nm FinFET CMOS

Abstract

An automatically placed-and-routed all-digital PLL for high-performance clock generation and distribution in many-core processors is presented. The proposed design leverages a phase domain architecture, and features an embedded TDC constructed from standard cells. TDC resolution is enhanced through the use of a phase interpolator. The standard cell library is extended with custom oscillator cells are designed to achieve optimized power, performance, and area. Timing and handling of potentially metastable paths is additionally handled by the digital design How. The clock generator has been fabricated in a 14-nm FinFET process, and occupies an area of 0.009 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The design features a tuning range from 1.0 to 5.5 GHz (80%). Output period jitter of 1.29 ps is achieved with a power consumption of 9.7 mW.