A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size

Abstract

As the first kind of forward error correction (FEC) codes that achieve channel capacity, polar codes have attracted much research interest recently. Compared with other popular FEC codes, polar codes decoded by list successive cancellation decoding (LSCD) with a large list size have better error correction performance. However, due to the serial decoding nature of LSCD and the high complexity of list management, the decoding latency is high, which limits the usage of polar codes in practical applications that require low latency and high throughput. In this paper, we study the high-throughput implementation of LSCD with a large list size. Specifically, at the algorithmic level, to achieve a low-decoding latency with moderate hardware complexity, two decoding schemes, a multibit double thresholding scheme and a partial G-node look-ahead scheme, are proposed. Then, a high-throughput VLSI architecture implementing the proposed algorithms is developed with optimizations on different computation modules. From the implementation results on United Microelectronics Corporation (UMC) 90 nm complementary metal oxide semiconductor (CMOS) technology, the proposed architecture achieves decoding throughputs of 1.103 Gb/s, 977 Mb/s, and 827 Mb/s when the list sizes are 8, 16, and 32, respectively.