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A 1.24 <inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>A Quiescent Current NMOS Low Dropout Regulator With Integrated Low-Power Oscillator-Driven Charge-Pump and Switched-Capacitor Pole Tracking Compensation
82
Citations
26
References
2018
Year
Low-power ElectronicsElectrical EngineeringEngineeringLow Dropout VoltageComputer EngineeringDropout VoltagePower ElectronicsTex-math Notation=Supply RegulationPower-aware Design
Supply regulation using low quiescent current linear regulators helps in extending the battery life of power aware applications with very long standby time. A 1.24 μA quiescent current NMOS low dropout (LDO) that uses a hybrid bias current generator (HBCG) which boosts the bias current dynamically and adaptively to improve the transient response is presented in this paper. A bias-current scalable error amplifier with an on-demand pull-up/pull-down buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. A novel switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA with a low-ESR 1 μF output capacitor. Designed in a 0.25 μm CMOS process, the LDO has an output voltage range of 1-3 V, a dropout voltage of 240 mV, and a core area of 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
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