A D-band CMOS power amplifier for wireless chip-to-chip communications with 22.3 dB gain and 12.2 dBm P1dB in 65-nm CMOS technology

Abstract

This paper presents a D-band linearized power amplifier (PA) with on-chip current combining transformer using a standard 65nm CMOS process, which covers 114 to 131 GHz. To mitigate the parasitic gate-drain capacitance feedback, each stage consists of common source (CS) amplifier with a neutralization using cross-coupled capacitor (Cc). The PA achieves a small-signal gain of 22.3 dB and 3-dB bandwidth (BW) of 17 GHz, a 1-dB compressed power (P1dB) of 12.2 dBm and a saturated output power (P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</inf> ) of 14.5 dBm with a peak PAE of 10.2%. The PA chip area is 0.343mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including the pads and the core chip area is 0.103mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .