A Digital Implementation of Extreme Learning Machines for Resource-Constrained Devices

Abstract

The availability of compact digital circuitry for the support of neural networks is a key requirement for resource-constrained embedded systems. This brief tackles the implementation of single hidden-layer feedforward neural networks, based on hard-limit activation functions, on reconfigurable devices. The resulting design strategy relies on a novel learning procedure that inherits the approach adopted in the Extreme Learning Machine paradigm. The eventual training process balances accuracy and network complexity effectively, thus supporting a digital architecture that prioritizes area utilization over computational performance. Experimental tests confirm that the design approach leads to efficient digital implementations of the predictor on low-performance devices.