A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator

Abstract

With advanced DAC switching [1-3] and low-power comparator [4] techniques, the successive-approximation register (SAR) ADC demonstrates convincing performance with technology development for internet-of-everything (IoE) applications. However, the power efficiency and accuracy of SAR ADCs over 12b are limited by DAC mismatch and comparator noise requirements, which increases by 4x for each additional 1b of resolution. Hybrid-SAR ADCs using sigma-delta modulators (SDMs) for fine conversion have been reported to reduce noise using oversampling and noise shaping operations with a power penalty from the required operational amplifier (opamp) for integrator realization. An integrator using a passive summing technique was reported [5] without using an opamp, however, the resulting gain loss degraded the effective resolution. This work presents a SAR-ISDM ADC with an opamp-less time-domain integrator without gain loss to effectively achieve a 13b resolution at 0.4V supply. An INL splitting (INLS) DAC switching scheme is also developed to achieve the lowest reported switching energy and improve the DNL/INL performance by 4x.