Temperature Compensation in CMOS Peaking Current References

Abstract

In this brief, modifications to the peaking current reference with MOS transistors operating in the subthreshold and the strong inversion region has been proposed by means of which very small currents with immunity to temperature variations on a chip can be obtained. Temperature compensation can be done by adding a source degeneration resistor to the conventional peaking current source structure. Design examples are provided for both weak and strong inversion operations with output currents of 1.5 μm and 40 μm with less than 4% and 10% variation over the span of -40 °C to +100 °C, respectively. A prototype of the circuit operating in the weak and strong inversion region is designed, simulated, and then fabricated in a TSMC 0.18-μm process. Measurement results verify the functionality of the proposed structure.