A 1.8-mW low power, PVT-resilient, high linearity, modified Gilbert-cell down-conversion mixer in 28-nm CMOS

Abstract

This paper presents a high linearity modified Gilbert-cell mixer designed for 60-GHz applications and fabricated in a 28-nm CMOS technology. To increase the linearity of the mixer, the RF transconductance stage was removed, thereby reducing the amount of stacked transistors. We propose using a self-biasing V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> reference in the bias network to make the mixer more robust to process-voltage-temperature (PVT) variations. Measurement results show that this mixer achieves a voltage conversion gain of 4.7 dB, a 1-dB compression point of -3 dBm and a 12.3 dB noise figure, while it draws only 2 mA from a single 0.9 V supply. The occupied area on the chip is 0.35×0.68 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including pads.