IEEE Transactions on Circuits & Systems II Express Briefs · 2018 · 26 citations · 8 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated CircuitsDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignCmos Analog Circuit DesignCmos Analog Integrated CircuitsCmos Digital Circuit DesignCmos Logic CircuitsDynamic RangeLinearityLogic GatesPower Consumption
A 6-bit 20 GS/s two-channel time-interleaved current-steering digital-to-analog converter (DAC) with compact full-binary sub-DACs is presented. Optimally adjusted transition timings between the input data and the interleaving clock minimize glitches by the time-interleaving switches and enhance the high-frequency linearity. In order to prevent static linearity degradation by the leakage current through the time-interleaving switches, the relationship between the output current and the leakage current is analyzed. The proposed DAC architecture and the pseudo-differential logic gates for the high-speed data interface reduce the circuit complexity as well as the power consumption. The prototype 6-bit 20 GS/s DAC, fabricated in a 65-nm CMOS process, achieves a spurious-free dynamic range of 35.1 dB up to the Nyquist input, and consumes 136 mW given a 1.2-V power supply.
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3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS
Ali Nazemi, Kangmin Hu, Delong Cui et al. · 2015 · 63 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory
Yuriy Greshishchev, D. Pollex, Shing-Chi Wang et al. · 2011 · 59 citations