A Fully On-Chip 80-pJ/b OOK Super-Regenerative Receiver With Sensitivity-Data Rate Tradeoff Capability

Abstract

This paper presents an ultra-low power superregenerative receiver suitable for ON-OFF keying modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40-nm CMOS technology and operates in the ISM band of 902-928 MHz. Binary search algorithm through successive approximation register architecture is being exploited to calibrate the internally generated quench signal and the working frequency of the receiver. Employing an on-chip inductor and a single ended to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 μW from a 0.65-V supply results in an excellent energy efficiency of 80 pJ/b at 4-Mb/s data rate (DR). The receiver also employs an analog to digital converter that enables soft-decisioning and a convenient sensitivity-DR tradeoff, achieving sensitivity of -86.5, and -101.5 dBm at 1000and 31.25-kbps DR, respectively.