An energy-efficient analog front-end circuit for a sub-1V digital hearing aid chip

Abstract

A low-power, energy-efficient analog front-end circuit is proposed and implemented for a digital hearing aid chip. It adopts the combined-gain-control (CGC) technique for an accurate preamplification and the adaptive-SNR (ASNR) technique for an improvement of dynamic range with low power consumption. The proposed analog front-end achieves 87-dB peak SNR and dissipates 60-/spl mu/W from a single 0.9-V supply. The core area is 0.5-mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.