A clock distribution network for microprocessors

TLDR

The clock distribution topology combines the advantages of tree and grid structures. The paper describes a global clock distribution strategy used on several microprocessor chips. The network uses buffered tunable trees feeding a common grid, with a new tuning method for the large interconnect modeled with 50,000 components, and variations for different floor‑planning styles. The strategy achieves global clock skew as low as 22 ps on large microprocessor chips.

Abstract

A global clock distribution strategy used on several microprocessor chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large microprocessor chips has been measured.