Burst Mode Optical Receiver With 10 ns Lock Time Based on Concurrent DC Offset and Timing Recovery Technique

Abstract

This paper describes a low-power, low-latency, 7–10  Gb/s burst-mode DC-coupled receiver for photonic switch networks. The receiver includes a transimpedance amplifier (TIA) followed by a three-stage differential amplifier. For burst-mode operation, DC and timing recovery loops work concurrently in the proposed architecture to achieve 5.8 ns lock time. The DC recovery loop employs a successive approximation algorithm to recover signal-dependent offset that takes only six cycles of C8 (1/8th of data rate) clock. The timing recovery uses a quarter-rate injection scheme that is immune to duty cycle distortion. The recovered clock jitter is 10 ps p-p for 10  Gb/s operation. The receiver consumes only 33 mW while operating at 10  Gb/s, and less than 2 mW (leakage power and bias circuit) during idle time. The completely inductor-less receiver occupies a 465  μm×265  μm area in 0.13 μm technology.