Channel-Adaptive ADC and TDC for 28 Gb/s PAM-4 Digital Receiver

Abstract

A low-power channel-adaptive 28 Gb/s PAM-4 receiver is presented utilizing a predictive analog-to-digital converter (ADC), a successive-approximation-register (SAR) time-to-digital converter (TDC), and a feed-forward equalizer (FFE) in the digital domain. The variable-resolution flash ADC takes advantage of the channel inter-symbol interference (ISI) and can achieve 5.5 bits resolution utilizing only 16 comparators. By reusing the comparators, the ADC can provide a programmable resolution from 2 to 5.5 bits consuming 40 to 90 mW, respectively. The SAR-TDC generates 5 bits timing information that includes 2 bits ISI and 3 bits timing error to achieve a low-latency and low-jitter timing recovery. Subsequently, a three-to-eight programmable tap FFE is used to equalize up to 30-dB loss achieving bit error rate lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> . FFE is implemented in a field-programmable gate array, and the first three taps are realized in a look-up table (LUT). An offline higher resolution ADC is used to generate the pre-computed values for the LUT. Measured power consumption is 130 mW (excluding digital signal processing) from a 1.2-V power supply with active chip area of 0.2025 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 65-nm technology. Due to programmability on the both ADC resolution and the number of FFE taps according to the channel loss, the receiver enables energy efficiency according to loss compensation.