Multi-level topology evaluation for ultra-efficient three-phase inverters

Abstract

Multi-level topologies reduce the requirements on inductors and filters, however, given the high number of series connected semiconductors, it is still unclear if they are a suitable option to achieve ultra-high efficiency while maintaining a reasonable power density. For this purpose, an extensive quantitative evaluation of different topologies is carried out, to determine the required volume for a targeted 99.5% efficiency of a 10kW three-phase inverter. This includes the EMI noise filtering, where the Common Mode filter is placed on the DC-side to save losses and the impact of the upcoming EMI regulations covering the range from 2 kHz to 150 kHz is discussed. With an evaluation of multilevel topologies, it is shown that even if a high number of levels can reduce the size of the magnetic components by an order of magnitude, the volume and losses of the capacitive components required to create the multi-level voltage output have to be considered. An evaluation is done to quantify the performance of topologies ranging from two-level to seven-level topologies, and detailed designs of the three-level T-type and seven-level Hybrid Active Neutral Point Clamped converters are presented, achieving a relatively high power density of 2.2 kW/dm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> and 2.7 kW/dm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> respectively.