A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS

Abstract

A non-interleaved 2-GS/s, 8-bit flash analog-to-digital converter (ADC) utilizing the remainder number system (RNS) quantization principle is presented. The RNS quantization reduces the number of comparators and thus improves the figure of merit of the flash ADC. A time-domain implementation is adopted to reduce the ADC input capacitance with a voltage-to-time converter (VTC) front end. The ring oscillator-based time-to-digital converter (TDC) also provides a linear and efficient modulo (folding) operation for the RNS quantization with built-in dynamic element matching. Offline TDC mismatch calibration based on a histogram (code density) test is also employed to further improve the ADC linearity. The prototype RNS ADC was fabricated in a 65-nm CMOS process with an active area of 0.08 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It measures an SNDR of 40.7 dB for a Nyquist input and an effective resolution bandwidth of 1.74 GHz.