Advancing CMOS-Type Ising Arithmetic Unit into the Domain of Real-World Applications

Abstract

Solving combinatorial optimization problems is a great challenge for Von Neumann-architecture computing. Although the Ising model could provide promising solutions for such problems, existing Ising chips, including superconductive, optical and CMOS-type circuit implementation, cannot meet the precision requirement of real-world combinatorial optimization applications. To facilitate the support for real-world applications, we propose three improvements over existing CMOS-type Ising chips: suitable narrow bit width memory cells with approximate multiply-adders, double random sources flipping method with cross random number generators and shared circuit design between adjacent spin nodes. With above improvements, we achieve high precision as well as maintaining the low cost characteristic of CMOS-type Ising chips. When searching the ground state of Ising models, our CMOS-type Ising chip can improve the precision to more than 99 percent over existing ones with about 93 percent precision. Moreover, its hardware cost is only 32 percent of the common implementation to achieve the same high precision. Specially, we have applied our Ising chip in image segmentation applications, a typical real-world application. The results show that, to find a segmentation with similar quality, our CMOS-type Ising chip can speed up the segmenting processing by 1900x with only 0.017 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> / <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">00</sub> energy consumption compared with approximate algorithms operating on conventional computers.