<i>V</i> _aq ‐based tri‐level switching scheme for SAR ADC

Abstract

An area‐efficient tri‐level switching scheme is proposed for the successive approximation register (SAR) analogue‐to‐digital converters (ADCs). Unlike existing tri‐level scheme, the proposed switching scheme is based on a new third reference voltage V aq which is a quarter of the reference voltage V ref . With reusing the least significant bit capacitors in the last two bits generation, the proposed switching scheme achieves 87.5% less number of unit capacitors and 96.48% less switching energy over the conventional scheme.