A 0.66e_rms⁻ Temporal-Readout-Noise 3-D-Stacked CMOS Image Sensor With Conditional Correlated Multiple Sampling Technique

Abstract

This paper presents a sub-electron temporal readout noise, 8.3 Mpixel and 1.1-μ pixel pitch 3-D-stacked CMOS image sensor (CIS). A conditional correlated multiple sampling (CMS) technique is introduced to selectively reduce the dark pixel noise by using a full-range ramp and a small-range ramp. In this way, a sub-electron temporal readout noise CIS is achieved without degrading the frame rate dramatically, compared to the conventional CMS method. A column-parallel single slope ADC with dark pixel detection function is proposed as well. A dynamic-dark-signal-region detection technique is used to mitigate differential nonlinearity (DNL) errors due to ramp slope mismatch. The implemented prototype in 45-nm CIS/65-nm CMOS occupies an area of 35.89 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This paper achieves a 0.66erms <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> with 5-time sampling at a frame rate of 7.2 frames/s, which corresponds to a sample-rate frequency of 36.1 kHz for the column ADC. The DNL (11 b) is improved from +0.98 LSB/-0.94 LSB to +0.29 LSB/-0.39 LSB by using dynamic dark-signal region technique. The figure of merit of this paper is 2.02 nVrms/Hz.