FPGA-based design of a self-checking TMR voter

Abstract

The most common error mitigation scheme used for hardening designs against radiation-induced upsets on FPGAs is Triple Modular Redundancy (TMR). In a TMR system, there are three copies of a module and voting circuits that mask errors by voting for the majority. There are several types of voting circuits which can be classified based on their insertion sites in the design, functionality or the type of data structure to be mitigated. These voters are mostly built from Look-up Tables (LUTs) but these voters just like the design that is hardened by applying TMR are also susceptible to radiation-induced effects. In this paper, we present the design of a self-checking LUT based 1-bit voter intended for those sites where a TMR system reduces to a duplex or a simplex system. Voters on these sites make a single point of failure and the proposed design avoids this situation by attaching multiple voter redundancies to the same output. The operation of the proposed voter has been verified through its hardware implementation and timing simulation.