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Second-Harmonic Current Reduction for Two-Stage Inverter With Boost-Derived Front-End Converter: Control Schemes and Design Considerations
135
Citations
26
References
2017
Year
Electrical EngineeringInfinite ImpedanceEngineeringVirtual Parallel ImpedanceVirtual Series ImpedanceBoost-derived Front-end ConverterPower Electronics ConverterTwo-stage InverterElectric Power ConversionSecond-harmonic Current ReductionPower InverterPower ElectronicsHarmonic Mitigation
The instantaneous output power of the two-stage single-phase inverter pulsates at twice the output frequency (2f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> ), generating notorious second-harmonic current (SHC) in the frontend dc-dc converter and the input dc voltage source. This paper focuses on the SHC reduction for a two-stage single-phase inverter with boost-derived front-end converter. To reduce the SHC, a virtual series impedance, which has high impedance at 2f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> while low impedance at other frequencies, is introduced in series with the boost diode or the boost inductor to increase the impedance of the boost-diode branch or boost-inductor branch at 2f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> . Meanwhile, for achieving good dynamic performance, a virtual parallel impedance, which exhibits infinite impedance at 2f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> while low impedance at other frequencies, is introduced in parallel with the dc-bus capacitor to reduce the output impedance of the boost-derived converter at the frequencies except for 2f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> . The virtual series impedance is realized by the feedback of the boost-diode current or the boost-inductor current, while the virtual parallel impedance is implemented by the feedback of the dc-bus voltage. Based on the virtual-impedance approach, a variety of SHC reduction control schemes are derived. A step-by-step closed-loop parameters design approach with considerations of reducing the SHC and improving the dynamic performance is also proposed for the derived SHC reduction control schemes. Finally, a 1-kW prototype is built and tested, and experimental results are presented to verify the effectiveness of the proposed SHC reduction control schemes.
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