A 0.8–1.2 V 10–50 MS/s 13-bit Subranging Pipelined-SAR ADC Using a Temperature-Insensitive Time-Based Amplifier

Abstract

This paper presents an energy-efficient 13-bit 10-50 MS/s subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) with power supply scaling. In the presented ADC, an SAR-assisted subranging floating capacitive DAC switching algorithm reduces switching energy along with enhanced linearity and speed in the first-stage SAR ADC. A following temperature-insensitive time-based residue amplifier realizes open-loop residual amplification without background calibration, while maintaining the benefits of dynamic operation and noise filtering. Furthermore, asynchronous SAR control logic employs a pre-window technique to accelerate SAR logic operations. The prototype ADC was fabricated in a 130-nm CMOS process with an active area of 0.22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With a 1.2-V power supply and a Nyquist frequency input, the ADC consumes 1.32 mW at 50 MS/s and achieves signal-to-noise and distortion ratio and spurious-free dynamic range of 69.1 and 80.7 dB, respectively. The operating speed is scalable from 10 to 50 MS/s with a scalable power supply range of 0.8-1.2 V. Walden FoMs of 4-11.3 fJ/conversion-step are achieved.