A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation

Abstract

A process, voltage, and temperature (PVT)-stabilized dynamic amplification technique is reported for the pipelined-successive-approximation-register (SAR) analog-to-digital converter (ADC). A non-interleaved 12-b 330-MS/s pipelined-SAR ADC prototype employing such technique achieves 0.5- and 0.8-dB signal-to-noise plus distortion ratio (SNDR) variations for supply voltage varying from 1.25 to 1.35 V and temperature varying from -5 °C to 85 °C, respectively. The corresponding residue gain variations are 1.5% and 1.2% under the same conditions, respectively. Moreover, 2-b/cycle SAR architecture together with the attenuated passive residue transfer technique is employed to boost the prototype conversion throughput significantly. Noise analyses of the attenuated passive residue transfer process and of the PVT stabilization circuit are also furnished. At 330 MS/s, the 65-nm CMOS prototype achieves an SNDR of 63.5 dB and a Walden FoM of 15.4 fJ/conversion step for a near-Nyquist input.