A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

TLDR

Neuromorphic systems use asynchronous event-driven neurons, offering high bandwidth and low power, yet scaling them is difficult because event traffic imposes significant circuit complexity and memory demands. The authors propose a routing method that blends hierarchical and mesh strategies with heterogeneous memory to reduce memory and latency while enabling flexible programming of diverse event‑based neural networks. They implemented and validated the scheme on a hybrid analog/digital multicore neuromorphic chip, providing theoretical analysis, circuit design, and characterization of the connectivity architecture. The prototype successfully ran a convolutional neural network for real‑time classification of visual symbols presented to a dynamic vision sensor at high speed.

Abstract

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.