Reducing Critical Configuration Bits via Partial TMR for SEU Mitigation in FPGAs

Abstract

This paper represents an single-event upset (SEU) hardened scheme for hardening circuits mapped onto field-programmable gate arrays (FPGAs). The proposed scheme calculates failure probability based on critical FPGA configuration bits and performs placement and routing to reduce the failure probability as much as possible. If the calculated failure probability is still greater than the required failure rate, partial triple modular redundancy is implemented to reduce critical configuration bits until the calculated failure probability is less than the required failure rate. The proposed scheme reduces area and power overhead and improves SEU vulnerability when compared with some previous schemes.