A 2GS/s 8b flash ADC based on remainder number system in 65nm CMOS

Abstract

A non-interleaved 2GS/s, 8b flash ADC achieves an effective resolution bandwidth (ERBW) of 1.74 GHz using a remainder number system (RNS) architecture, which results in reduced number of comparators while preserving the flash speed of the converter. The prototype ADC, fabricated in a 65nm CMOS process with an area of 0.08 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , achieves an SNDR of 40.7 dB for a Nyquist input. The measured DNL and INL are ±0.14 and ±0.61 LSBs, respectively.