A 13b-ENOB 173dB-FoM 2^nd-order NS SAR ADC with passive integrators

Abstract

This paper presents a low-power 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order noise-shaping (NS) SAR ADC. Instead of using power-hungry op-amps, it uses switches and capacitors to make passive integrators for noise shaping. The overall architecture is simple and the NS order can be easily reconfigured from 0 to 2. A prototype chip is fabricated in a 40nm CMOS process. With 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order NS, the chip consumes 143μW power at 1.1V and 8.4MS/s. At an OSR of 16, SNDR is 80dB and the Schreier FoM is 173dB.