Energy‐efficient higher‐side‐reset‐and‐set switching scheme for SAR ADC

Abstract

A high energy‐efficiency higher‐side‐reset‐and‐set (HSRS) switching scheme for a successive approximation register (SAR) ADC is presented, which consumes zero switching energy for the decision of the first two most significant bits without using any auxiliary circuit. The proposed HSRS scheme achieves 92.2% savings in switching energy and 50% reduction in total capacitance compared with a conventional SAR.