A novel 700V deep trench isolated double RESURF LDMOS with P-sink layer

Abstract

A novel DTI double RESURF LDMOS with P-sink layer is presented and experimentally demonstrated in this paper. The novel structure features a P-sink layer around the bottom of deep trench, which is formed with the Deep N-type Well (DNW) after the process of high temperature driving in. The highly doped P-sink layer restrains the extension of depletion region along the horizontal direction, improving the isolation performance. According to the simulation results, the surface electric field peak of the proposed DTI LDMOS is reduced by 35 % due to the enhanced depletion effect of P-sink layer. Meanwhile, the concentration of DNW and P-top region are increased, thus the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on, sp</sub> is decreased. Furthermore, the isolation region area is reduced significantly so that the chip size will be minimized. The LDMOS with R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on, sp</sub> of 96.2 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and BV of 758 V is experimentally achieved, which breaks the conventional R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on, sp</sub> -BV silicon limit of double RESURF technology.