Replacing copper interconnects with graphene at a 7-nm node

Abstract

We examine graphene for interconnects within a 7-nm FinFET technology. Multiple scenarios considered alter dimensions and/or materials to reflect realistic graphene interconnect fabrication. Replacement is restricted up to the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> BEOL metal layer (M3) as graphene is advantageous over copper in terms of resistivity only for line widths <; 30 nm. Initial standard-cell level analysis is extended to benchmarking of a commercial 32-bit processor for the most promising graphene interconnect scenario: horizontally oriented graphene interconnects with bulk resistivity (ρ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> ) of 1.5 μΩ-cm and stack height (h) of 20 nm. Full-chip energy-delay-product (EDP) improves up to ~8% as the shorter graphene stack height reduces parasitic capacitances. We also consider the impact of graphene contact resistance on via resistances: although via resistance increases as much as 20×, low performance targets still demonstrate EDP improvement, suggesting further potential improvement from electronic design automation (EDA) tool optimization.