A Nanosecond-Transient Fine-Grained Digital LDO With Multi-Step Switching Scheme and Asynchronous Adaptive Pipeline Control

Abstract

This paper introduces a multi-step switching scheme for a digital low dropout regulator (DLDO) that emerges as a new way of achieving nanosecond-transient and fine-grained on-chip voltage regulation. The multi-step switching scheme takes advantage of the adaptive pipeline control and asynchronous clocking for area- and power-efficient digital controller utilization. It speeds up the transient response by varying the pass transistor sizing in two available lengths of coarse steps as per the perturbation, while maintaining a small output voltage ripple by toggling in a finer step at steady operation. A prototype proving the proposed concept, i.e., a 0.6-1.0-V input, 50-200-mV dropout, and 500-mA maximum loading DLDO with an on-chip 1.5-nF output capacitor, is fabricated in a 65-nm CMOS process to verify the effectiveness of this scheme. By employing the multi-step switching scheme and adaptive control, the DLDO achieved a fast transient response to nanoseconds loading current change, and a 100 mV per 10-ns reference voltage switching, as well as a resolution of 768 levels ( <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">~</sub> 9.5 bits) with a 5-mV output ripple. The quiescent current consumed by this DLDO at steady operation is down to 300 μA .