Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM

Abstract

In the spin-transfer-torque random access memory design, the sensing scheme has become a bottleneck from the viewpoints of performance and read energy, because the required read current and time are too large to satisfy a target read yield. When the target read yield is greater than the fundamental read-yield limit determined by bit-to-bit data-cell variation, the conventional data-cell-variation-tolerant (DCVT) sensing scheme cannot satisfy the target read yield without requiring impractically high performance and energy overhead. To resolve this problem, this paper proposes a DCVT dual-mode sensing scheme (DMSS) that operates mostly in normal mode when correct sensing is assured, and infrequently in exception mode when correct sensing is uncertain. Using the dual-mode strategy, the DMSS can achieve the target read yield, while significantly mitigating the performance and energy overhead. Monte-Carlo HSPICE simulation results, using industry-compatible 45-nm model parameters, show that the proposed DMSS achieves a read yield of 6.1 sigma with a 3.2× faster read time and 4.5× lower read energy than the destructive self-reference sensing scheme.