Influence of Channel Thickness Variation on Temperature and Bias Induced Stress Instability of Amorphous SiInZnO Thin Film Transistors

Abstract

TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage (<TEX>$V_{TH}$</TEX>) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (<TEX>${\Delta}V_{TH}$</TEX>) increased steadily, with increasing channel thickness. These results can be explained by the total trap density (<TEX>$N_T$</TEX>) increase due to the increase of bulk trap density (<TEX>$N_{Bulk}$</TEX>) in a-SIZO channel layer.