Large-Area CVD-Grown Sub-2 V ReS₂ Transistors and Logic Gates

Abstract

We demonstrated the fabrication of large-area ReS₂ transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS₂ semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS₂ channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS₂ transistors with graphene electrodes decreased dramatically compared with the SiO₂-devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm²/(V s) and an on/off current ratio exceeding 10⁴. NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS₂ semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.