A 0.4% PAE 194-GHz Signal Source With 1.5-mW Output Power in 65-nm Bulk CMOS Technology

Abstract

This letter presents an amplifier-frequency doubler chain in thin digital 65-nm bulk CMOS process. Injection locking is applied to the amplifier to increase the power gain and compensate for the conversion loss in the frequency doubler. The doubler uses a compact low-impedance transmission line (LZ TLine) for effective dc decoupling in the output matching network. Measurement results show a peak output power of 1.5 mW at 194 GHz, and a peak PAE of 0.4% at 196 GHz. The locking range is measured as 8.5 GHz (92.5~101 GHz) with 2-dBm input fundamental power, and can be extended to 15 GHz with 4-dBm input power.