Fast and Flexible Successive-Cancellation List Decoders for Polar Codes

TLDR

Polar codes are a leading coding scheme for 5G, and successive‑cancellation list decoding offers a good trade‑off between error‑correction performance and hardware complexity, but its throughput is limited, while simplified variants SSCL and SSCL‑SPC accelerate decoding by eliminating redundant calculations for specific bit patterns. The authors aim to reduce the number of bit estimations required by SSCL and SSCL‑SPC while preserving error‑correction performance. They introduce Fast‑SSCL and Fast‑SSCL‑SPC algorithms that limit estimations based on list size and present hardware architectures achieving 1.86 Gb/s throughput. The new algorithms allow tuning of estimations to.

Abstract

Polar codes have gained significant amount of attention during the past few years and have been selected as a coding scheme for the next generation of mobile broadband standard. Among decoding schemes, successive-cancellation list (SCL) decoding provides a reasonable trade-off between the error-correction performance and hardware implementation complexity when used to decode polar codes, at the cost of limited throughput. The simplified SCL (SSCL) and its extension SSCL-SPC increase the speed of decoding by removing redundant calculations when encountering particular information and frozen bit patterns (rate one and single parity check codes), while keeping the error-correction performance unaltered. In this paper, we improve SSCL and SSCL-SPC by proving that the list size imposes a specific number of bit estimations required to decode rate one and single parity check codes. Thus, the number of estimations can be limited while guaranteeing exactly the same error-correction performance as if all bits of the code were estimated. We call the new decoding algorithms Fast-SSCL and Fast-SSCL-SPC. Moreover, we show that the number of bit estimations in a practical application can be tuned to achieve desirable speed, while keeping the error-correction performance almost unchanged. Hardware architectures implementing both algorithms are then described and implemented: it is shown that our design can achieve 1.86 Gb/s throughput, higher than the best state-of-the-art decoders.