1e:T435,In this paper, a neuromorphic crossbar circuit with binary memristors is proposed for speech recognition. The binary memristors which are based on filamentary-switching mechanism can be found more popularly and are easy to be fabricated than analog memristors that are rare in materials and need a more complicated fabrication process. Thus, we develop a neuromorphic crossbar circuit using filamentary-switching binary memristors not using interface-switching analog memristors. The proposed binary memristor crossbar can recognize five vowels with 4-bit 64 input channels. The proposed crossbar is tested by 2,500 speech samples and verified to be able to recognize 89.2% of the tested samples. From the statistical simulation, the recognition rate of the binary memristor crossbar is estimated to be degraded very little from 89.2% to 80%, though the percentage variation in memristance is increased very much from 0% to 15%. In contrast, the analog memristor crossbar loses its recognition rate significantly from 96% to 9% for the same percentage variation in memristance.1f:T4c9,Using memristor devices as synaptic connections has been suggested with different neural architectures in the literature. Most of the published works focus on simulating some plasticity mechanism for changing memristor conductance. This paper presents a neural architecture of a character recognition neural system using Al/Pr _0.7 Ca _0.3 MnO ₃ (PCMO) memristors. The PCMO memristor has an inhomogeneous barrier at the aluminum and PCMO interface which gives rise to an asymmetrical behavior when moving from high resistance to low resistance and vice versa. This paper details the design and simulations for solving this asymmetrical memristor behavior. Also, a general memory read/write framework is used to describe the running and plasticity of neural systems. The proposed neural system can be produced in hardware using a small 1 K crossbar memristor grid and CMOS neural nodes as presented in the simulation results.20:T4f0,In this paper, we propose a new twin crossbar architecture of binary memristors for low-power image recognition. In the new twin crossbar, we use two identical memristor arrays instead of using the previous complementary memristor arrays of M ⁺ and M ^- . Thereby, we can apply the discrete cosine transform (DCT) algorithm to reduce the number of low-resistance state (LRS) cells in the two identical M ⁺ arrays. With the reduced number of LRS cells in two M ⁺ arrays, the power consumption in the crossbar can be significantly saved compared to the previous complementary crossbar that is not suitable to DCT. When the number of discarded coefficients in the DCT matrix is 56.25%, 67.19%, 76.56%, and 84.38%, the power consumption of the new twin crossbar is reduced by 51.7%, 61.3%, 69.9%, and 77.4%, respectively, compared to the previous complementary one.

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