IEEE Transactions on Circuits & Systems II Express Briefs · 2017 · 56 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsClock ManagementCmos Circuit DesignHigh-frequency Power ConversionLow-power Digital Circuit DesignRenewable Energy Power ConversionCharge Pump DesignCharge-pump ConvertersClock DesignClocking SchemesEnergy HarvestingEnergy Harvesting IntegrationEnergy Harvesting SystemsLow-voltage Cmos Design
This brief reports a compact and fully integrated three-stage charge-pump (CP) scheme with a 1:10 step-up ratio for energy-harvesting applications. To undertake a low-voltage input (e.g., from thermoelectric or solar source), our CP scheme features a differential bootstrapped ring-VCO generating sixphase clock signals with a boosted swing. Driven by replicas of these swing-boosted clock signals, the entailed number of CP stages is reduced and a 1:10 step-up ratio can be achieved with only a 3-stage CP, resulting in a higher PCE. Using the replicas of the clock signals also reduces substantially the dependency of the clock frequency on the load drivability. Fabricated in 65-nm CMOS, a 0.87-V output voltage is measured at a 38.8% power conversion efficiency, under a 500-kΩ load and a 0.15-V input. The chip area is 0.032 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
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