An Energy-Efficient and Low-Crosstalk Sub-THz I/O by Surface Plasmonic Polariton Interconnect in CMOS

Abstract

Traditional TEM-based I/O communication through either PCB traces or free space has significant path loss and electromagnetic (EM) interferences that are hardly employed toward low-power and dense I/Os for data server. We propose a 0.1-1 THz or sub-terahertz (THz) I/O interface using surface plasmonic polariton (SPP) interconnects in CMOS to obtain high-energy efficiency and low-crosstalk interconnect. The surface wave can be established with on-chip generation and further deployed for signal propagation by corrugating periodical grooves onto the traditional transmission line. It will result in a strongly localized electromagnetically wave onto the surface of top-layer metal in wideband, leading to the broadband low EM coupling between many core and memories. Moreover, we have also developed a high on/off ratio split-ring-resonator-based modulator to support the sub-THz I/O communication. The proposed SPP interconnect achieves data rate of 25 Gb/s with 0.016 pJ/b/mm energy efficiency at 140 GHz in 65-nm CMOS. In addition, two surface-wave channels placed with 2.4-μm spacing exhibits an average -28-dB crosstalk ratio.