20.6 A 0.5V-V<inf>IN</inf> 1.44mA-class event-driven digital LDO with a fully integrated 100pF output capacitor

Concepts

EngineeringElectrical EngineeringCircuit TheoryLow-power DesignSystem-on-chip DesignCmos Circuit DesignVoltage RegulatorsLow-power Cmos DesignOutput Voltage RegulationPower DensitySystem-on-chip ArchitectureSystem-on-chip Integration

Abstract

In today's system-on-chip designs, a low-drop-out voltage regulator (LDO) is one of the most popular choices to create a distinct voltage domain owing to its high power density. Many LDOs, however, need a large output capacitor (C OUT ) to compensate a fast load current (I LOAD ) change, increasing the number of pins and off-chip components. In synchronous digital LDO designs, high frequency can miniaturize C OUT , but it inevitably causes power inefficiency [2]. A recent work has instead employed an event-driven (ED) control scheme to alleviate the C OUT requirement, demonstrating a 400μA-class digital LDO with a C OUT of 400pF [1]. The ED scheme is promising, but it is still desirable to develop an LDO which can support a larger I LOAD with a smaller C OUT . This is indeed a daunting challenge since a substantial reduction in feedback latency (T LAT ) is necessary to retain the same level of output voltage change (ΔV OUT ) with a smaller C OUT . In this work, to shorten latency, we propose to infuse fine-grained parallelism into ED control systems and develop a fully integrated digital LDO. The prototyped LDO can support 1.44mA I LOAD at 0.5V V IN , 0.45V V SP , and 99.2% peak current efficiency. The LDO shows less than 34mV (7.6%) ΔV OUT with a 0.1nF C OUT when ΔI LOAD is ±1.44mA.