An Energy-Efficient DAC Switching Method for SAR ADCs

Abstract

This brief presents a capacitor switching technique to reduce the power consumption in successive approximation register (SAR) analog-to-digital converters (ADCs). The proposed method ideally does not consume any switching energy in digital-to-analog converter and for a 10-bit ADC; it achieves 87% reduction in the total capacitor area compared to the conventional SAR ADC. In addition, the accuracy of the proposed SAR ADC does not depend on the accuracy of the mid-level reference voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm</sub> ). Moreover, the common-mode input voltage of the comparator will remain constant. The proposed ADC is simulated in a 90-nm CMOS technology with sampling rate of 100 kS/s and resolution of 10-bit. The simulation results achieve an 8.5 effective number of bits with about 0.5-μW power consumption resulting in a FoM of 9.76 fJ/conversion-step.