Linear CMOS $LC$ -VCO Based on Triple-Coupled Inductors and Its Application to 40-GHz Phase-Locked Loop

Abstract

A linear CMOS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> voltage-controlled oscillator (VCO) utilizing triple-coupled inductors and a 40-GHz integer-N phase-locked loop (PLL) are fabricated in a standard 90-nm CMOS process. The VCO utilizes triple-coupled inductors to couple varactor pairs, which compensate each other to linearize the VCO gain. The triple-coupled <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> tank is theoretically analyzed using equivalent circuit models. With the triple-coupled inductors, there is no need for tuning-voltage shifting circuits or dc-block capacitors, suitable for high-performance millimeter-wave (mm-wave) VCO design. A 40-GHz PLL has also been design and built around this linear <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> -VCO to demonstrate a stable PLL with small loop bandwidth variations. The measured tuning bandwidth, phase noise, and figure of merit (FOM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula> ) of the linear VCO is 15.8%, −100.7 dBc/Hz at 1-MHz offset, and −181.8 dBc/Hz, respectively. Utilizing the linear VCO, the experimental PLL is stably locked from 38.61 to 44.55 GHz. The PLL without output buffer consumes 76 mW from 1.5/1.0 V supplies. The measured in-band and out-band phase noise of the 40-GHz PLL are −81 dBc/Hz at 100-kHz offset, and −114.5 dBc/Hz at 10-MHz offset, respectively. Thanks to the proposed linearization method, the VCO gain shows very small variations, compared with reported works. The implemented PLL demonstrates good stabilities with small loop bandwidth variations across the operation frequency range.