Pattern Recognition Using Carbon Nanotube Synaptic Transistors with an Adjustable Weight Update Protocol

TLDR

Efficient computing systems with low energy consumption are needed, and neuromorphic hardware inspired by brain parallelism offers a promising solution, but synaptic device implementation is hindered by uncontrollable weight updates that limit system optimization. We aim to demonstrate a synaptic transistor built from highly purified, pre‑separated 99 % semiconducting carbon nanotubes that offers adjustable weight‑update linearity and variation margin. We validate the pattern‑recognition performance using a device‑to‑system level simulation framework that incorporates the CNT‑based transistor. The increased variation margin, rather than linearity alone, improves fault tolerance and boosts recognition accuracy.

Abstract

Recent electronic applications require an efficient computing system that can perform data processing with limited energy consumption. Inspired by the massive parallelism of the human brain, a neuromorphic system (hardware neural network) may provide an efficient computing unit to perform such tasks as classification and recognition. However, the implementation of synaptic devices (i.e., the essential building blocks for emulating the functions of biological synapses) remains challenging due to their uncontrollable weight update protocol and corresponding uncertain effects on the operation of the system, which can lead to a bottleneck in the continuous design and optimization. Here, we demonstrate a synaptic transistor based on highly purified, preseparated 99% semiconducting carbon nanotubes, which can provide adjustable weight update linearity and variation margin. The pattern recognition efficacy is validated using a device-to-system level simulation framework. The enlarged margin rather than the linear weight update can enhance the fault tolerance of the recognition system, which improves the recognition accuracy.