A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15ps SAR-TDC

Abstract

This paper introduces a first-order noise-shaped time-domain ADC utilizing SAR-TDC as quantizer. The high resolution correlated double sampling SAR-TDC improves the quantization noise level of the ADC. The VCO non-linearity is resolved by employing a 1-bit folded VCO architecture. The ADC linearity is further improved using foreground digital calibration. Implemented in 65nm CMOS, the 675MS/s time-domain ADC achieves measured peak SNDR/SFDR of 79.5/86.4dB in 10MHz BW while consuming 11.65mW. The SAR-TDC achieves 1.15ps resolution with peak measured DNL/INL of 0.64/0.65LSB. The 1-bit folded VCO improves the VCO linearity from 12% to 0.17%.