2016 · 16 citations · 12 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice ModelingDevice SimulationIntegrated Circuit DesignMemory DevicesMemory ModelingSemiconductor ReliabilityCompact Device ModelingCompact ModelingDesign ConstraintsMemory ArraysMemory Circuit DesignMemory Device SimulationNon-ideal EffectsPhysics-based Device Modeling
A novel compact model is developed by coupling comprehensive physical equations from electrical, thermal and phase-transition domains in order to capture their correlations that exist in GeSeTe (GST) device physics. Several non-ideal effects during GST-based memory cell operations have been studied with particular focus on cell Read/Write margins and reliability issues. Finally, large-scale 3-D cross-point memory array circuits have been simulated with developed physics-based models to further explore the design constraints.
12
H.‐S. Philip Wong, Simone Raoux, Sang‐Bum Kim et al. · Proceedings of the IEEE · 2010 · 1.8K citations