Microprocessor realization of a linear predictive vocoder

Abstract

A microprocessor realization for a linear predictive vocoder is presented. The goal was a low-power, low-cost, compact special-purpose realization of a narrow-band speech terminal. The resultant design is a general-purpose two-bus structure running at a 150 ns cycle time, using as the basic signal processing element, four of the AMD 2901 CPE chips. This basic structure is augmented by a four-cycle multiplier to allow for sufficient signal processing power. The design concessions that mark the linear predictive coding microprocessor (LPCM) as a special-purpose machine designed to be a speech terminal are: limited I/O and limited memory. The present design requires 162 dual-in-line packages, dissipates less than 45 W and occupies about <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\frac{1}{3}</tex> ft <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .