A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Modulator

Abstract

A time-to-digital converter (TDC) is proposed to re- place the multi-bit quantizer and the multi-bit feedback DAC of traditionalvoltage-mode modulator.Sincetime-modesystems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ADC digital friendly and more suitable for nano- metrictechnologies.Apulse-width-modulator(PWM)convertsthe sampled-and-held voltage-sample to a digital pulse whose width is proportional to the voltage level of the sample. Then, the TDC gen- erates a digital code that corresponds to the pulse width. Simulta- neously, the TDC provides a time-quantized feedback pulse for the modulator, emulating the voltage-DAC in a conventional ADC.Linearity,jitteranddata-dependent-delayeffectsontheper- formance of the proposed architecture are analyzed. A chip proto- typeis fabricated in TI 65 nmdigitalCMOS process. THD of 67 dB is achieved which corresponds to a TDC's DNL of less than 0.8 ps without calibration. Measurements show that the -modulator achievesadynamicrangeof68dBandtheTDCconsumes5.66mW at 250 MHz event rate while occupying 0.006 mm .